This invention relates to computer systems in which peripheral units are interconnected with a CPU via an I/O bus.
Many computer systems are known which employ a bus arrangement for enabling communication between a CPU and peripheral units, such as floppy disk or hard disk storage devices. Such systems all require some arrangement or technique for identifying which particular peripheral units are attached to the bus and for assigning bus addresses to individual units uniquely, in order to avoid conflict or ambiguity during I/O read and write operations.
With the increasing popularity of computers for business office and home uses, the trend in the design of computer systems has been to simplify the initial system set up procedure and also to facilitate reconfiguration of the system, for example by replacement of a limited storage device at a subsequent time by a storage device of greater capacity or by adding on more storage devices to an initial basic system configuration. Whenever such a system is initially set up, and also when such a system is reconfigured, an initial routine is typically provided in order to determine that each connected device has been allotted memory location on the bus and also to determine that each device is operational. This procedure normally requires that the bus-connected devices have a switch selectable bus base address in order to fit into the memory scheme imbedded into the computer system. Such an arrangement lacks flexibility and is difficult for non-skilled users to implement in the field, which frequently necessitates initial set up by a skilled technician.